A digital-to-analog converter (DAC) converts a digital input word to an analog output signal. DACs typically operate in either a unipolar or bipolar mode. The generic equation for determining the output VOUT in unipolar and bipolar DACs is shown in Equation 1:
                              V          OUT                =                  G          *                      V            REF                    *                      (                                          K1                *                                                      INPUT                    ⁢                                                                                  ⁢                    CODE                                                        2                    n                                                              -              K2                        )                                              (        1        )            
where INPUT CODE is an n-bit digital word, G is the gain of the DAC and K1 and K2 are constants that determine the configuration mode. In unipolar mode configuration (e.g., when the output varies from 0 volts to VREF), K1=1 and K2=0 so that VOUT varies between 0 and G*VREF. In bipolar mode configuration (e.g., output varies from −VREF to VREF), K1=2 and K2=1 so that VOUT varies between −G*VREF and G*VREF. For the inverting unipolar configuration K1=−1 and K2=0 so that VOUT varies between 0 and −G*VREF.
FIG. 1 shows the example of a well known architecture of an inverting unipolar 3-bit DAC 10, which receives input VREF, control signal UPDATE and digital input INPUT CODE, and generates analog output VOUT. The DAC of FIG. 1 has 3-bit resolution (i.e. n=3) for illustration only and can easily be modified to any practical resolution desired. The digital input INPUT CODE is a 3-bit digital word used by DAC 10 to convert input VREF into analog output VOUT. UPDATE is a binary control signal which determines when the digital word INPUT CODE can be used to convert VREF to produce a new VOUT. When UPDATE is LOW, VOUT remains substantially constant. When UPDATE changes from LOW to HIGH, DAC 10 converts VREF to analog output VOUT based on the digital input INPUT CODE.
DAC 10 comprises resistor ladder 12, switches 161, 162 and 163, switch compensation element 174, switch control block 18, op-amp 22 and feedback element 20. Resistor ladder 12 is of a type commonly called an R-2R ladder, and includes substantially identical fixed resistors 2311 to 2342 and substantially identical trim structures 3011 to 3042. The input VREF is applied to input node 1 of DAC 10 while the output VOUT is produced at output node 3. An additional DAC node referred henceforth as GROUND is used as reference potential for both input VREF and output VOUT.
Resistor ladder 12 receives the input VREF on node 1, is connected to switches 161, 162 and 163 through nodes 151,152 and 153, respectively, and to switch compensation element 174 through node 154. It comprises a number of switched and series branches. The first switched connected in series, and is coupled between input node 1 and node 151. It functions as the most significant bit (MSB) of the ladder. The first series branch comprises fixed resistor 2313 and trim structure 3013, connected in series, and is coupled between input node 1 and network and two trim structures 3021 and 3022, all connected in series, and is coupled between internal node 4 and node 152. It functions as the second bit of the ladder. The second series branch comprises fixed resistor 2323 and trim structure 3023, connected in series, and is coupled between internal node 4 and internal node 5. The third switched branch comprises two fixed resistors, 2331, and 2332, and two trim structures 3031 and 3032, all connected in series, and is coupled between internal node 5 and node 153. It functions as the least significant bit (LSB) structures 3041 and 3042, all connected in series, and is coupled between internal node 5 and node 154. It functions as the ladder termination and is connected to GROUND through the switch resistance compensation element 174.
In describing an R-2R ladder, the series branches are conventionally called the R-branches, and the switched branches and the termination branch are called the 2R-branches.
Switch control block 18 receives control input UPDATE and digital input INPUT CODE. When UPDATE changes state from LOW to HIGH, switch control block 18 adjusts the states of switch control nodes 281 through 283, according the present value of INPUT CODE. In this example of a 3-bit DAC, INPUT CODE will be a 3-bit binary signal. When the most significant bit (MSB) of INPUT CODE is HIGH, the switch control 18 will set node 281 directing switch 161 to couple node 151 to node 2. When the most significant bit (MSB) of INPUT CODE is LOW, switch control 18 will set node 281 directing switch 161 to couple node 151 to GROUND. Similarly, a HIGH or LOW state in the second bit of INPUT CODE will result in switch control 18 setting node 282 directing switch 162 to couple node 152 to node 2 or GROUND respectively. A HIGH or LOW state in the third, least significant bit (LSB), of INPUT CODE will result in switch control 18 setting node 283 directing switch 163 to couple node 153 to node 2 or GROUND respectively. In the manner described, the digital input INPUT CODE in combination with input VREF causes an intermediate current, IDAC to flow into node 2 from the switch elements 161 to 163 according to Equation 2, where RDAC is the input impedance of the R-2R ladder:
                                                                        I                DAC                            =                                                (                                                            V                      REF                                                              R                      DAC                                                        )                                *                                  (                                                            INPUT                      ⁢                                                                                          ⁢                      CODE                                                              2                      n                                                        )                                                                                                        =                                                (                                                            V                      REF                                                              R                      DAC                                                        )                                *                                  (                                                            INPUT                      ⁢                                                                                          ⁢                      CODE                                        8                                    )                                                                                        (        2        )            Feedback element 20 and op-amp 22 form a current-to-voltage converter. The op-amp 22 has an inverting input terminal (−) coupled to node 2, a non-inverting input terminal (+) coupled to GROUND, and an output terminal coupled to node 3. Feedback element 20, coupled between node 2 and node 3, creates a feedback loop around the op-amp 22.
Feedback element 20 comprise fixed resistor 24, trim structure 31, and switch resistance compensation element 175, all connected in series. The total resistance of feedback element 20 is commonly referred to as RFB.
The current to voltage converter operates to convert intermediate current IDAC into output voltage VOUT. The resulting VOUT is described by Equation 3:
                                                                        V                OUT                            =                            ⁢                                                -                                      I                    DAC                                                  *                                  R                  FB                                                                                                        =                            ⁢                                                -                                      V                    REF                                                  *                                  (                                                            R                      FB                                                              R                      DAC                                                        )                                *                                  (                                                            INPUT                      ⁢                                                                                          ⁢                      CODE                                                              2                      n                                                        )                                                                                                        =                            ⁢                                                -                                      V                    REF                                                  *                                  (                                                            R                      FB                                                              R                      DAC                                                        )                                *                                  (                                                            INPUT                      ⁢                                                                                          ⁢                      CODE                                        8                                    )                                                                                        (        3        )            
For the 3-bit DAC example, MAX INPUT CODE=23−=7.
When DIGITAL INPUT=0:
                VOUT=0V, corresponding to ZERO SCALEand when DIGITAL INPUT=7:        
            V      OUT        =                  -                  V          REF                    *              (                              R            FB                                R            DAC                          )            *              (                  7          8                )              ,corresponding to FULL SCALE
From equation (3), the value of VOUT is scaled by the ratio RFB/RDAC. Comparing equations (3) and (1) it is immediate that G=(RFB/RDAC). A common choice for a unipolar DAC is G=1 requiring RFB=RDAC. It is highly desirable for ratio G to be accurate, stable with respect to external factors like temperature, time, etc. and have minimal pre-trim errors. Thus it is common practice to maintain, with a high degree of accuracy, the same ratio G between constituent structures of the same type contained in feedback element 20 and ladder 12. Toward this goal corresponding feedback element and ladder components of same type (i.e. fixed resistors, trim structures and switches) are implemented using mutually identical unit components with good matching properties.
FIG. 2 shows a known bipolar DAC 110 comprising current converter 40, reference inverting circuit 114, offset resistive element 125, op-amp 22 and feedback element 120. DAC 110 receives input VREF, control signal UPDATE and digital input INPUT CODE and generates analog output VOUT. The input VREF is applied to input node 8 of DAC 110 while the output VOUT is produced at output node 3.
The reference inverting circuit 114, comprising op-amp 140 and gain resistors 142 and 144 is configured as a standard inverting buffer amplifier. It has an input terminal coupled to input node 8 and an output terminal connected to internal node 1. Input gain resistor 142 is connected between node 8 and the inverting input of op-amp 140 while feedback gain resistor 144 is connected between output and inverting input of op-amp 140. The non-inverting input of op-amp 140 is connected to GROUND. The output of op-amp 140 is connected to internal node 1. The reference inverting circuit 114 serves to produce an inverted VREF (i.e., −VREF) signal at node 1. The Current Converter 40, coupled between internal nodes 1 and 2 is described in detail in FIG. 1.
Alternatively, amplifier 140 and resistors 142 and 144 could be external to signal processor 110 in the signal path.
The offset resistive element 125, coupled between input node 8 and internal node 2, has an internal structure similar to feedback element 20 comprising a fixed resistor structure, a trim structure, and a switch resistance compensation element, all connected in series. The total resistance of offset resistive element 125 is referred to as ROFFSET.
Feedback element 120 and op-amp 22 form a current-to-voltage converter. The op-amp 22 has an inverting input terminal (−) coupled to node 2, a non-inverting input terminal (+) coupled to GROUND, and an output terminal coupled to node 3. Feedback element 120, coupled between node 2 and node 3, creates a feedback loop around the op-amp 22. Feedback element 120 has similar internal structure as previously described feedback element 20, and comprises a fixed resistor structure, a trim structure, and a switch resistance compensation element, all connected in series. The total resistance of feedback resistor element 120 is referred to as RFB.
In the same manner described above for DAC 10 of FIG. 1, the digital input INPUT CODE in combination with the input signal present at node 1 causes an intermediate current, IDAC to flow into node 2 from the converter 40 according to Equation 4, where RDAC is the input impedance of the R-2R ladder and the signal on node 1 is −VREF:IDAC=(−VREF/RDAC)·(INPUT CODE/2n)  (4)
A second signal path from input node 8 through offset resistive element 125 to node 2 causes a second intermediate current, IOFFSET to flow into node 2 according to Equation 5:IOFFSET=(VREF/ROFFSET)  (5)
The current to voltage converter operates to convert the sum of the intermediate currents IDAC and IOFFSET to the output VOUT. The resulting VOUT is described by Equation 6:VOUT=−(IDAC+IOFFSET)·RFB =VREF[(RFB/RDAC)*(INPUT CODE/2n)−(RFB/ROFFSET)]  (6)
For a 3-bit DAC example, 2n=8 and MAX INPUT CODE=23−1=7.
Thus for DIGITAL INPUT=0:VOUT=−VREF·(RFB/ROFFSET)And for DIGITAL INPUT=7:VOUT=VREF*[(RFB/RDAC)*(⅞)−(RFB/ROFFSET)]
From equation (6), the value of VOUT is scaled by the ratio RFB/RDAC and is offset by the ratio RFB/RDAC. By comparison to equation (1), as K2=1 for a bipolar DAC, it results:(RFB/ROFFSET)=1ThereforeRFB=ROFFSET 
By further comparison to equation (1) it results:G=(RFB/RDAC)/K1A common choice for a bipolar DAC is G=1, resulting inRFB=2*RDAC 
To maintain an accurate transfer function for DAC 110 as given by equation 6, it is therefore highly desirable for ratios RFB/RDAC, and RFB/ROFFSET to be accurate, stable with respect to external factors like temperature, time, etc. and have minimal pre-trim errors. Thus it is common practice to maintain, with a high degree of accuracy, the same ratio between constituent structures of the same type contained in feedback element 120 and current converter 40. Toward this goal, corresponding feedback element and current converter components of same type (i.e. fixed resistors, trim structures and switches) are implemented using mutually identical unit components with good matching properties. Furthermore it is common practice to maintain, with a high degree of accuracy, the same ratio between constituent structures of the same type contained in feedback element 120 and offset resistive element 125. Toward this goal, corresponding feedback element and offset resistive element components of same type (i.e. fixed resistors, trim structures and switch resistance compensation structures) are implemented using mutually identical unit components with good matching properties.
DAC 110 shows one technique for applying opposite polarity to the current converter and to the level shift structure, a condition which is required for this type of bipolar DAC. However, other suitable techniques for establishing this condition are well-known in the art.
The prior art includes various configurations of DAC 10 and DAC 110 in monolithic or discrete form. The configurations are typically chosen to be unipolar, bipolar or a combination thereof, such as a software programmable signal processor of a type described in U.S. Pat. No. 6,310,567, incorporated herein by reference.
A person skilled in the art will be familiar with resistor ladder 12 and other versions of R-2R ladder networks, and will be aware that R-2R ladders are classic and widely employed examples of networks whose transfer functions depend primarily on the ratio matching of identical unit elements of the constituent structures.
Errors in resistor ladder 12, current converter 40, feedback elements 20 and 120 and offset resistive element 125 are caused by the resistances and switches in each of the branches not matching or ratioing exactly. It is common practice to use mutually identical unit resistors like fixed resistors 2311 through 2342 of resistor ladder 12 when implementing such networks in order to minimize matching errors. Nevertheless, matching errors between identical fixed elements are inherent in any practical implementation and result in transfer function linearity errors. The problem is usually alleviated by connecting adjustable structures like trim structures 3011 through 3042 in series with fixed resistors. Such trim structures can be adjusted in calibration processes such as to correct residual mismatch of the fixed elements. In order to further reduce mismatch errors it is common practice to use trim structures which are mutually identical prior to any trimming and to associate a trim structure to every fixed element in the network. In this manner every constituent structure of the network has the same ratio between the value and number of fixed elements to trim structures
Mismatch between different branches of resistor ladder 12 produce Linearity Errors in the DAC transfer function and are adjusted using the built-in trim structures 3011 through 3042. Errors in RFB/RDAC ratio introduce a gain error in transfer functions of both unipolar DAC 10 and bipolar DAC 110 commonly called Gain Error. Errors in RFB/ROFFSET ratio introduce an undesired offset in transfer function of bipolar DAC 110 commonly called Bipolar Offset Error. Gain Errors and Bipolar Offset Errors must be corrected in a calibration process in the same manner as Linearity Errors.
For unipolar DAC 10 the Gain Error is commonly adjusted using the trim structure contained by feedback element 20. For bipolar DAC 110 the Gain Error is commonly adjusted using the trim structure contained by feedback element 120. Similarly the Bipolar Offset Error of DAC 110 is adjusted using the trim structure contained by the offset resistive element 125.
When trim structures are adjusted by laser trimming of fuse links or other common techniques their value typically can only be increased. Thus, when Linearity Errors are reduced using the trim structures 3011 through 3042, the ladder equivalent impedance RDAC is increased thus changing the ratio RFB/RDAC and producing a Gain Error. Due to this undesired interaction the Gain Error adjustment must be performed after the Linearity Error adjustment.
For the bipolar DAC 110, a change in value of RFB during Gain Error adjustment modifies the ratio RFB/ROFFSET and thus produces a Bipolar Offset Error. Therefore for a bipolar DAC a Linearity Error adjustment must be followed by a Gain Error adjustment and subsequently by a Bipolar Offset Error adjustment.
A problem will occur in implementing this adjustment sequence if, following a Linearity Error correction, the ratio RFB/RDAC is higher than desired. Because the value RFB can only be increased through the adjustment process it is not possible to directly lower the ratio RFB/RDAC. This suggests the option of increasing the value of RDAC. However, with resistor networks commonly used in implementing DACs, a change in RDAC will directly result in Linearity Errors. In addition many practical adjustment means, including laser trim, can be used one time only on any given trim structure. Therefore, once linearity trimming is completed it is generally not possible to make any further adjustments to the trim structures 3011 through 3042. Thus the Gain Error adjustment is, for all practical purposes, a “unidirectional trim” able to correct only a negative Gain Error and must be performed after Linearity Error adjustments.
A common solution for this problem is to introduce a systematic negative pre-trim Gain Error so large that it will remain negative following the worst case Linearity Error adjustment. This strategy has significant undesirable consequences. It requires a substantial increase in the trim range resulting in substantially larger trim structures. Due to the “worst case” design target most DACs will need to by adjusted by large amounts resulting in excessively long trim time and increased likelihood of post-trim drift.
Another common solution is to add a “look-ahead” calculation and additional skew trim within the linearity trim procedure such as to insure that the Gain Error will remain slightly negative following Linearity Error adjustment. According to this strategy attempts are made to predict the resulting Gain Error at intermediary steps in the Linearity Error adjustment and corrective skew trims are applied. While preferable to the previous solution, this approach has its own undesirable consequences. The prediction process requires complex measurements and calculations which together with the additional skew trim operations substantially increase the overall adjustment time. Moreover additional trim range is still necessary forcing an increase in size for certain trim structures. An increase in size for some trim structures results in a size increase for all trim structures because, in order to reduce pre-trim matching errors, the use of mutually identical structures is highly desirable. Furthermore the prediction algorithm is complex and imperfect thus not always effective.